IMPLEMENTATION OF LOW-POWER AND AREA-EFFICIENT 64BIT CARRY SELECT ADDER

Now a day’s hottest area of research in VLSI system is design of the area, high-speed and power-efficient data path logic systems. All processor consisting of Arithmetic & logical Unit (ALU) and adder plays an important role for design of ALU. In digital adders, the speed of addition is limited by the time required to send a carry through the adder. Carry Select Adder (CSLA) is an efficient is used for data-processing processors to perform fast arithmetic functions. The proposed work reduces area and power consumption to a great extent with the help of a simple ripple carry adder (RCA) and gate-level architecture. Regular CSLA consist of two RCA and proposed design has been projected by single RCA. This improves the performance of the proposed designs then the regular designs in terms of power consumption and area.