Validation of state machine specifications

The paper presents a new view on the quality assurance of state machine programs. Instead of the term “verification of state machine programs”, it is proposed to use the terms “verification of state machine models” and “validation of state machine specifications”. The first of which is applicable in the presence of a formal specification, and the second — in its absence, which is more typical for practice. This allows a more meaningful approach to understanding how to ensure the quality of state machine programs.