VHDL IMPLEMENTATION OF HIGH SPEED AXI2.0 PROTOCOL WITH DDR3 CONTROLLER

This paper proposes the implementation of AXI 2.0 protocol which removes the limitation of communication architecture, which would otherwise reduce the speed of data transfer in System - on - Chip (SoC). We have also implemented DDR3 controller which was then interface with AXI 2.0 protocol. Proposed protocol was synthesized on Xilinx 13.1 and simulated using Modelsim 6.5e.