Implementation of Regular Linear Carry Select Adder with Binary to Excess-1 Converter

Regular Linear Carry Select Adder (RCSLA) is one of the fastest adders. From the structure of RCSLA, there is scope to reduce area by using Binary to Excess-1 converter (BEC) technique. By using BEC technique in RCSLA 16, 32, 64 bit architectures have been developed and compared with Regular Linear Carry Select Adder. The modified architectures have reduced area and power with slight increase in delay. Simulation and Synthesis are carried on Xilinx ISE 12.2.The result analysis shows that the modified architectures are better than RCSLA.