Design and Evaluation of Pulse Triggered Flip-Flop Based on Split Output TSPC Latch for Low Power High Performance Digital Circuit

In this paper a Pulse Triggered Flip-Flop based on Split Output TSPC Latch suitable for low power high performance application is proposed. The Pulse Triggered Flip-Flop is constructed using a split output TSPC latch with embedded logic. Proposed flip-flop has the advantages of simple structure, less number of transistors, low dissipation power and lower transistor area. Proposed circuit is simulated in cadence analog design environment with 0.25?m CMOS technology. Simulation results show that by using the proposed circuit, dissipation power can be reduced by 40%, number of transistors by 40%, current drawn by 48% and transistor area can be reduced by 68%.