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Journal: International Journal of Application or Innovation in Engineering & Management (IJAIEM) (Vol.4, No. 8)

Publication Date:

Authors : ; ;

Page : 141-146

Keywords : Keywords:- Discrete Wavelet Transform(DWT); Inverse Discrete Wavelet Transform(IDWT); Field programmable Gate Array(FPGA); Very Large Scale Integration(VLSI);

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ABSTRACT This paper studies the implementation of VLSI Architecture of image compression system using wavelet. Discrete wavelet transform is the most widely used image compression technique and it is the most efficient algorithm used in JPEG image compression. An architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed Conventional method requires more memory, area and power, lifting scheme is used as an enhanced method. Architecture of the DWT which is a powerful image compression algorithm is implemented using lifting based approach. This architecture results in reduced memory referencing¸ low power requirement¸ low latency and high throughput. The Inverse Discrete Wavelet Transform (IDWT) is also obtained in a similar way to get back the image matrix. The design can be used for both lossy and lossless compression. To reduce the complexities of the design, linear algebra view of DWT and IDWT has been used[1] . The advantages of the proposed architecture are the hardware optimization, fast computing time, regular data flow and reduce complexity. Because of the regular structure, the proposed architecture can be easily be scaled with the filter length and 2D DWT level. VLSI architecture for the 2-D DWT is implemented using FPGA in VHDL. With the growing popularity of the applications that use large amounts of image and video coding is an active and dynamic field. . Image and Video Compression for Multimedia Engineering gives a basis for research and development

Last modified: 2015-09-15 15:05:22