Comparison of Noise, Power and Delay of Different Multiplier’s using Variable Threshold MOSFET in 45nm Technology

ABSTRACT In the modern time designing a circuit that consumes less power with minimum delay and noise is one of the major challenges. Normally the circuits are design in CMOS technology. But we know Dynamic Threshold MOSFET (DTMOS) consumes less power than CMOS as it is operated in sub-threshold region and the leakage current is used for its computational operation. Now to reduce the power consumption further and achieve an ultra-low power region of operation Variable Threshold MOSFET (VTMOS) is introduced. In this paper we design a Baugh Woley, Braun and Vedic Multiplier using VTMOS calculated its noise, power and delay in T-spice and a comparison of those circuits with the conventional CMOS design has been done. The circuits have also been implemented by Xilinx 10.1.