HARMONIC REDUCTION AND VOLTAGE DIP MITIGATION USING P-Q THEORY CONTROLLED STATCOM

ABSTRACT This paper presents seven level inverter based Static compensator (STATCOM) for Harmonic reduction (HR) in source current and to mitigate the voltage dip. The Asymmetric seven level inverter (ASLI) is simulated using two H-bridge cells with each cell having four ideal switches. The compensating reference current is estimated using instantaneous active and reactive power (pq) theory which is fast acting and instantaneous. For generating gate signals for seven levels inverter variable switching frequency sub-harmonic pulse width modulation (VSFSHPWM) is used due to its simplicity and easy implementation. The seven level inverter based STATCOM is simulated using MATLAB/SIMULINK and the results are presented. The results shown that the shunt compensation current injected active and reactive power of STATCOM effectively and decreased the harmonics in source current due to nonlinear harmonic producing load and it also mitigated the voltage dip occurring in the system due to 3-phase fault.