CURRENT STARVED VCO DESIGNED USING 70NM CMOS PROCESS

Current starved VCO is simple ring oscillator consisting of cascaded current starved inverters. This paper gives a performance evaluation of five staged Current Starved VCO on simulating tool Tanner 13.0 using 70nm CMOS Process Tech nology. Performance evaluation is done in terms oscillation frequency, average power consumption, and tuning range. The Frequency has been enhanced up to 2.6011GHz at 1.8V DD with low power consumption of 170uW. The tuning range in five stage current starv ed VCO is come out to be high ranging from 0.1 to 1.8V. This design is highly suitable for PLL applications. Therefore, a robust VCO can be designed for reliable operation. The techniques proposed in this paper can also be applied to other low voltage an alog and RF circuits to improve their performance.