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Journal: International Journal OF Engineering Sciences & Management Research (Vol.3, No. 4)

Publication Date:

Authors : ; ; ;

Page : 19-226

Keywords : Test compression; automatic test equipment (ATE); design - for - testability (DFT); intellectu p al property (IP)core; system - on - chip (SOC) test.;

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Est vector compression is an emerging trend in the field of VLSI testing. According to these trends, increasing test data volume is one of the biggest challenges in the testing industry. In order to reduce on - chip storage as well as testing time ,the large volume of test data input is compressed in hybrid manner before being downloaded into the processer. Test compression involves comp ressing the large volumes of test data to small test sets that fit in the memory of Automatic Test Equipment. As the density of VLSI circuit increases, high test quality in smaller geometries can be achieved only through more test patterns. So it is essent ial to integrate dedicated test logic on a chip called Automatic Test Equipment for testing. But this tester has limited speed, memory and I/O channels. The test data bandwidth between the tester and the chip is small which is the bottleneck in determining how fast the testing process. To overcome these limitations of the Automatic Test Equipment (ATE), a new hybrid test vector compression technique is proposed. The test compression ratio is increased and is experimentally verified with the benchmark circui ts.

Last modified: 2016-04-25 22:54:57