Switching Techniques: Concepts for Low Loss Switching

Highlighting the dominance & supremacy of CMOS digital logic design over its counterparts & further coming up with a unique solution to minimize the power losses prevalent in switching implementations using CMOS, this brief introduces a novel SDLC (Switching-DiodeInductor-Capacitor) design. It presentsa design which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In traditional CMOS logic design, energy is stored in a load capacitor when the output is high & it dissipates this stored energy during low level output. Attempt has been made to harness this discharging energy by storing it inside an inductor in the form of magnetic fieldin the proposed SDLC architecture. This significantly reduces the switching dissipation energy. The proposed SDLC architecture has been illustrated via MULTISIM software simulation. A brief description of existing logic design implementations and scope for future research in this domain has also been discussed in this paper.