Traffic and Power reduction Routing Algorithm for NOC Cores

With the progress of VLSI technology, the number of cores on a chip keeps increasing, Now a days we are increasing the processing level of the chip, NOC is a best method to interconnect the core with each other core on the chip, it reducing the overall chip power and Traffic level by sharing the work load with other cores on the chip. And Dynamic Voltage Frequency Scaling (DVFS) is the technique for monitoring the Frequency/Voltage level of each core of the chip and providing sufficient power to the cores, ATPT is a Table that having (low and high) Frequency level table of the Each core. ATPT has very high prediction accuracy system. Depends upon the data speed of the core the voltage/frequency will be given by DVFS. If the core is in ideal state for a while, that core is moved to low power mode. So the power of the each core will be reduced.