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Conditional Capturing System for Low Power Clock Distribution Networks

Journal: International Research Journal of Advanced Engineering and Science (Vol.1, No. 2)

Publication Date:

Authors : ; ;

Page : 135-138

Keywords : CMPFFE; current mode; low power clock distribution; pulse logic; skew;

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Low-power design is becoming a crucial design objective due to the growing demand on portable applications and increasing difficulties in cooling and heat removal. A clock distribution network (CDN) delivers the clock signal which act as a reference to all sequential elements in the synchronous systems. The clock distribution network consumes a considerable amount of power in electronic devices. The proposed conditional capturing method for clock distribution using current is used to distribute a global clock. Further a pulsed logic is adapted to reduce the power consumption. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals. When the CMPFFE is combined with pulsed logic, the design results in lower average power compared to traditional voltage mode clocks.

Last modified: 2016-07-09 16:13:23