Asynchronous Domino Logic Pipeline Based ECRL

This project presents a high-throughput and ultralow-power asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain or gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits are greatly simplified, which offers the pipeline high throughput as well as low power consumption. Moreover, the stable critical data path enables the adoption of single-rail domino gates in the noncritical data paths. This further saves a lot of power by reducing the overhead of logic circuits. An 8 × 8 array style multiplier is used for evaluating the proposed pipeline method. Compared with a hybrid ? rail asynchronous domino logic pipeline, the proposed ECRL pipeline consumes less power and also reduces no of transistor used.