Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register Tanner

This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.