Analysis and Design of Low Power Dynamic Memory using FVD and SPD Methods

Dynamic gates are one of the critical circuits in RWD path of high speed memory. However these dynamic gates have poor noise immunity and their switching activity consume significant power. In this paper two dynamic domino circuits are proposed that reduce power consumption and delay at the output node. That is Footed node voltage domino method (FVD) and Switching Pulse domino method (SPD). These circuits prevent the leakage current and unwanted clock pulse during their high switching activity in precharge phase. Simulation is done by cadence virtuoso analog environment tool using 180nm technology and calculated power, delay, and speed of proposed circuit and compared results with existing domino method for power and clock frequency. This proposed domino method reduces power consumption and delay compare to standard and existing domino logic method. These circuits are placed in read out path of memory.