IUL-cache: Infrequently Utilized Line Policy to Achieve Low-leakage L2 cache

ABSTRACT The significant leakage power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. To alleviate power limit issue, this paper proposes an adaptive dynamic voltage scaling (DVS) with cache line utilization frequency to reduce unnecessary dissipated leakage power for L2 cache. While modern microprocessor adopts a high cache capacity as well as associativity, those approaches are inefficient for power dissipation. However, considerable cache liens are not utilized and it senseless wastes leakage power. Thus, proposed model could identify the infrequently utilized lines and adaptively changes the level of supplied voltage to the cache lines. The dynamic access frequency detector employs a counter based algorithm to classify infrequently utilized lines according to the different types of access pattern with SPEC2K benchmarks analysis. As a result, the proposed IUL-cache scheme achieves 25% PDP improvement compared to the decay-cache and 45% PDP improvement compared to the conventional cache.