HARDWARE IMPLEMENTATION OF CRYPTOSYSTEM BY AES ALGORITHM USING FPGA

ABSTRACT Advanced Encryption Standard (AES) is an approved cryptographic Algorithm that can be used to protect electronic data. The Advanced Encryption Standard can be programmed in software or built with hardware. However Field Programmable Gate Arrays (fpgas) offer a quicker, more customizable solution, hence we used the FPGA as for implementation purpose. We show how a modified structure in these Hardware devices results in significant improvement of the design efficiency. The conventional scheme of AES is vulnerable for cryptanalysis. Static S-Boxes are implemented using look up tables which will never vary with the input text or input key. This consumes a lot of Memory for the storage of look up table. Thus it is essential to generate S-Bytes at run time. It is beneficial if the S-byte generated during run time varies with the input key. Another weakness of AES is that it works with a single key. In this paper, a new scheme of AES involving generation of Key based SBoxes and dual key AES is proposed. This overcomes the vulnerability of static S-Boxes and also single key encryption scheme.