Performance Analysis Of Low Power Using Hybrid And Subthreshold Adiabatic Logic For Digital Circuit

ABSTRACT By using CMOS logic and transmission gate logic, a hybrid 1-bit full adder is designed, which is reported in this paper. The design is first implemented for 1-bit full adder and then extended for application of 4-bit Ripple Carry Adder(RCA).The Modification in the 4-bit Ripple Carry Adder is done by using Subthreshold adiabatic logic(SAL) circuits.It is analyzed to make great improvement in ultra low power circuit design. When comparing with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power.After the implementation, the comparison of power is made between Hybrid logic and the Subthreshold adiabatic logic for 4-bit Ripple Carry Adder.Hence, 18% of power is reduced using SAL logic. The circuit is simulated using Cadence Virtuoso tool in 180nm technology.