9T SRAM Cell with Improved Self-Controllable Voltage Level Circuits

As the feature size of the transistor is scaled down, the threshold voltages of MOSFETs have been reduced thereby leakage power substantially increases. Furthermore, leakage is the only source of energy consumption in an idle circuit. A 0.25μm 9T SRAM which provides low leakage power is designed in this paper. A new leakage current reduction circuit called a “improved Self-controllable Voltage Level (SVL)” circuit is developed and included to reduce the leakage power of 9T SRAM. Simulation result of 9T SRAM with improved SVL design using TANNER tool shows the reduction in total average power. The Tanner T-spice simulation in standard 0.25μm CMOS technology confirms all results obtained for this paper.