Development of Verification Tool for Minimal Boolean Equation
Journal: IEEE Technology and Engineering Education (ITEE) (Vol.8, No. 4)Publication Date: 2013-12-30
Authors : Afaq Ahmad; Diede Ruelens; Saad Ahmad;
Page : 1-6
Keywords : Boolean function minimization; Combinational circuits; Logic gates; MATLAB;
Abstract
A MATLAB based tool is developed to verify the correctness of computed minimal Boolean equations. The development of this tool is stemmed from the fact that the performance of digital circuit can be increased to an optimum level by reducing number of literals in Boolean function. There exist various approaches towards reduction of literals to a minimum. However, before translating the minimal solution into hardware it is further required to verify the result and this is the objective of this paper. Since MATLAB provides such an opportunity where a common student, instructor and educational institution can get easy access with their limited resources and therefore, we preferred to develop this tool on MATLAB platform.
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