Design and Implementation of High Speed Signed Multiplier Using 3_2 Compressor

Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets ? high speed, low power consumption, regularity of layout and hence less area for compact VLSI implementation. Multiplier is based on the ancient algorithms (sutras) for multiplication [1]. This work is based on one of the sutras called Urdhava Tiryakbhyam. These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes less area. This paper presents a technique to modify the architecture of the Urdhava Tiryakbhyam by using compressor in order to reduce area and delay to improve overall performance. The coding is done for 16 bit(Q15), 32 bit(Q31) and 64 bit(Q63) fractional fixed point multiplications using Verilog HDL and Synthesized using Xilinx ISE version 9.2i. The performance is compared in terms of area, delay with earlier existing architecture of Vedic multiplier. The proposed design shows very good improvements in terms of area and time delay