Error Detection and Enhanced Decoding of Different Set Codes for Memory Applications

The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. Reliability, Availability and Serviceability are the three important parameters to be satisfied by any application. With further reduction in transistor size that leads to smaller dimensions, higher integration densities, and lower operating voltages, the reliability of memories is put into jeopardy. Single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. A new approach to design fault-secure encoder and decoder circuitry for memory designs is introduced. The parity-check Matrix of an FSD-ECC (fault secure detector - error correcting code) has a particular structure that the decoder circuit, generated from the parity-check Matrix, is Fault-Secure. LDPC codes satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries.