HIGH THROUGHPUT CACHE CONTROLLER USING VHDL & IT’S FPGA IMPLEMENTATION

The world is now using multicore processors for development, research or real-time device purposes as they provide a better processing leading to better performance. This has attracted a number of researchers as the processors are embedded on a single chip and the performance can be easily amplified by saving the space, reducing power consumption, reducing the delay of the system. In the past years, a lot of technique shave emerged which proposes the optimization. One such important scope of optimization is the cache handling which has a considerable effect on the power, performance, and area of the processor. The problem with the cache which has to be overcome is the coherence which needs to be implementing to design a suitable and efficient technique. In this paper a new concept from which the cache controller is designed using the least recently used (LRU) cache replacement policy