Design of an Area Efficient Three Input XOR/XNOR Circuit using Systematic Cell Design Methodology

The use of XOR–XNOR circuits has been the topic of numerous reports in the form of full adder circuits, compressors, parity checkers and comparators. In most of these systems, XOR/XNOR gates constitute a part of the critical path of the system, which significantly affects the overall performance of the system. An optimized design is desired to avoid any degradation on the output voltage, consume less power, and have a less number of transistors to implement the circuit. Two different designs for 3-input exclusive-OR (XOR) function at transistor level with a systematic cell design methodology (SCDM) are proposed in this paper. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. The proposed designs have low dynamic and short-circuit power consumption and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. These designs are used to improve the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. In this paper, we designed three input XOR/XNOR circuits by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and transistor count with respect to other designs.