Limiting The Data Hazards by Combining The Forwarding with Delay Slots Operations to Improve Dynamic Branch Prediction in Superscalar Processor

Modern microprocessor performance has been significantly increased by the exploitation of instruction level parallelism (ILD). Continued improvement is limited by pipeline hazards, due to data dependency between instructions in sequential programs. Many operations proposed in previous studies, such as delay slots and forwarding separately, to avoid occurrence of data dependency such as Architectural Tradeoffs in the Design of MIPS-X, rewriting executable files to measure program behavior. In this paper we will introduce a new mechanism to use a combination of these operations together to avoid the data hazard that causes degradation to performance of ILP.