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Design of Low Power and Area Efficient Full Adder for ALU Using 90nm Process for Industrial Based CAD/CAM Manufacturing Units

Journal: International Journal of Mechanical and Production Engineering Research and Development (IJMPERD ) (Vol.7, No. 6)

Publication Date:

Authors : ; ;

Page : 71-78

Keywords : CMOS; GDI; Hybrid full adder; CPL;

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The research article shows a high accuracy of full adder with less zone and power utilization. The GDI based full adder wasactualized by utilizing both entryway dispersion through input gate diffusion system and rationale pass transistor that reduces the area and power. To reduce the static power, ultralow control diode was utilized. The leakage current of the diode exists in scope of pA. The experimental work has been done through existing framework like CMOS, CPL and cross breed full adders with a proposed full adder. Every full adder was composed with gpdk 0.90 um in Cadence Virtuoso schematic and simulations were done in a Specter Simulator..

Last modified: 2018-01-13 18:10:44