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OPTIMIZATION OF DIGITAL COMPARATOR USING TRANSMISSION GATE LOGIC STYLE
Journal: International Journal of Advanced Research in Engineering and Technology (IJARET) (Vol.7, No. 4)Publication Date: 2016-08-29
Authors : Mukherjee D.N. Panda S.and Maji B.;
Page : 06-16
Keywords : Digital comparator; CMOS logic; transmission logic gate; power consumption; delay; transistor count;
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Abstract
In the present scenario low power, speed and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement of digital comparator the usage of proposed transmission gate logic method and compared in terms of power consumption, propagation delay and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 0.25-micrometer technology.
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Last modified: 2018-04-06 20:02:16