Design of Radix- 4 Signed Digit Encoding for Pre- Encoded Multipliers Using Verilog

In this paper, we introduce an architecture of pre-encoded multipliers for digital signal processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 SignedDigit (NR4SD) encoding technique, which uses the digit values f1; 0; þ1; þ2g or f2; 1; 0; þ1g, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.