Design and Implementation of Memory Block using SRAM

CMOS technology feature size and threshold voltage have been scaling down for decades for achieving high integration density and high performance. The continuing decrease in the aspect ratio and the corresponding increases in chip density and operating frequency have made power consumption a major concern in VLSI design. This paper provides the outline structures of Static Random Access Memory (SRAM) for low power dissipation with 6T AND 8T SRAM. The reason for attaining low power in the SRAM is by reducing the voltage at output node. The memory block of 4 BIT using 8T designed by 90nm technology with supply voltage of 1.2V. It is implemented by using synopsys tool using custom compiler.