A LOW JITTER – LOW PHASE NOISE WIDEBAND DIGITAL PHASE LOCKED LOOP IN NANOMETER CMOS TECHNOLOGY

In this article innovative low jitter low phase noise 7.47 GHz DPLL with self-aligned DLL in 180 nm CMOS technology is implemented and analyzed. Based on proposed innovative concept, phase difference between injection signal and SILVCO in PLL can be aligned to reduce jitter and phase noise over all variations. Hence it can be achieved low phase noise and low jitter. At 7.47 GHz, the measured phase noise of proposed DPLL with self-aligned injection at 1-MHz offset is 124.40 dBc/Hz with a rms jitter of 110 fs. The total dc power consumption is 27.72 mW. With self-aligned injection, proposed DPLL features the lowest jitter, phase noise, and best figure of merit among reported CMOS PLLs