Design of Floating Point Arithmetic Logic Unit with Universal Gate

A floating point arithmetic and logic unit design using pipelining is proposed. By using pipeline with ALU design, ALU provides a high performance. With pipelining plus parallel processing concept ALU execute multiple instructions simultaneously. Floating point ALU unit is formed by combination of arithmetic modules (addition, subtraction, multiplication, division), Universal gate module. Each module is divided into sub-module. Bits selection determines which operation takes place at a particular time. In this design of universal gate perform logical operation such as AND,OR,NOT,NOR,NAND operation also in this work area and delay parameter are reduces. The design is and validated using vhdl simulation in the xilinx13.1i software.