Hardware Realization of Low Complexity Video Encoder within Distributed Video Coding Framework

Distributed Video Coding is a new solution for video surveillance because of its low complexity of the encoder. This paper introduces Distributed Video Coding theory and traditional DVC framework, and come out a hardware realization on FPGA and gives optimization methods. This paper uses integer transformation instead of DCT to reduce the computational complexity and change the organization of bit-planes to reduce the latency. The results of experiments show that the Wyner-Ziv codec has similar rate-distortion performance to H.264 Intra codec while the temporal complexity of WZ codec is 10 times less than H.264 Intra codec. The hardware usage of WZ encoder is only 1/3 of H.264 encoder and shows the superiority of low complexity of encoder.