AN ENTROPY BASED GENETIC ALGORITHM TO SIMULTANEOUSLY MINIMIZE AREA AND WIRE LENGTH FOR VLSI FLOOR PLANNING PROBLEM

Due to the exponential increase in number of components on a VLSI (Very Large Scale Integration) chip over the years, there is a need to develop automated algorithms to decide the relative positions of circuits on a chip. In order to improve the performance of a chip, it is essential to deal with multiple objectives including area and wire length during the floor planning phase. Genetic Algorithms can be effectively used for multi objective optimization to generate optimal floor plans. In this paper, to solve the floor planning problem entropy based genetic algorithm is proposed to minimize area and wire length simultaneously using a heuristic placement strategy. The heuristic placement strategy helps in deciding the positions of rectangular modules on a chip. Microelectronics Centre of North Carolina (MCNC) benchmarks circuits are used to test the performance of our algorithm. Experimental results show that our algorithm can generate competitive solutions in comparison with various techniques proposed in literature for outline-free floor plans.