Semiconductor IC Package Leakage Current Improvement

This technical paper presents the improvement in the leakage current performance of Semiconductor Integrated Circuit (IC) packages by eliminating the Electrostatic Discharge (ESD) events during assembly process and ensuring the proper machine grounding and ESD controls. It is of high importance to significantly reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding. After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm. Continuous improvement enhances the quality of the product, which also lowers the risk of having potential customer complaint in the future.