Chip-On-Lead Semiconductor Package with Copper Wirebonding

This technical paper presents a systematic way of addressing critical challenges during introduction of Chip-On-Lead (COL) semiconductor package specifically wirebonding issues that leads to production dilemma during production ramp-up of products using Copper wire in tapeless leadframe. The project was intended to determine the “Red-X” or the major cause of yield detractors that may lead to quality issue during wirebonding process. Problem solving tools are showcased in this paper such as data analysis, cause and effect, Design-of–Experiment (DOE) and mechanical dimensional analysis, which provided significant impact in determining the real root-cause of the problem. Step-by-step elimination of variables is achieved with the use of statistical engineering tools. Outcome of the project eliminated the occurrence of Non-Stick-On-Pad (NSOP) during wirebonding process without cost involved and just optimizing the available in-house resources. The improvement enhanced the quality of the product after final test, which in turn lowered the risk of having potential customer complaint in the future.