Design of Modified Booth Multiplier using Reversible gate logic for Radix-8

This paper describes the concept of multiplication by using modified booth algorithm and reversible logic functions for radix-8. By using Modified booth algorithm, less delay is produced compared to normal multiplication process. This booth algorithm also reduces the number of partial products which will reduce maximum delay count at the output. Reversible logic has the advantage of reducing the gate count, garbage outputs as well as constant inputs. Results are compared with Radix-2 and Radix-4 Booth multiplier. This modified booth algorithm is synthesized and simulated by using Xilinx 8.1 ISE simulator and ModelSim.