Implementation of Charge Leakage and Sharing Noise Susceptible Dynamic CMOS Design

Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. In this paper, we proposed a PMOS and NMOS keeper logic to improve the voltage transitions in dynamic gates. This keeper circuit technique is proposed in this paper for simultaneous power reduction and speed enhancement of dynamic logic circuits. The threshold voltage of the keeper transistor is modified during circuit operation to reduce the contention current without sacrificing noise immunity.