Power Optimization in Domino Circuits using Stacked Transistors

In this work low leakage and high noise immunity domino circuit is analysed. Usually power and noise immunity are optimized at the expense of reduced speed. The domino circuit described has negligible speed degradation. The circuit improves the noise immunity by comparing the pull up network current with the worst case leakage current. The logic implementation network is separated from the keeper transistor by current comparison stage in which the current of the pull up network is compared against the worst case leakage current. The contention between the keeper transistor and pull down network is greatly reduced by this method. The dynamic node is isolated from logic implementation network and hence the parasitic capacitance on the dynamic node is greatly reduced. Since capacitance is reduced the loss in speed due to additional transistors is compensated. Because of reduced parasitic capacitance small keepers are enough to design faster circuits. A footer transistor is employed in diode configuration which further reduces leakage current.