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DSP Architecture for Wireless Sensor Nodes Using VLSI Technique

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 2)

Publication Date:

Authors : ;

Page : 883-891

Keywords : Digital processor; parallel prefix; wireless sensor network (WSN).;

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Abstract

Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element, the energy consumption can be significantly reduced. This paper describes the design and implementation of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware. Measurements of the silicon implementation show an improvement of 10?20× in terms of energy as compared to traditional modern micro-controllers found in sensor nodes.

Last modified: 2014-08-27 21:15:19