Wideband and Low Power CMOS Analog Multiplier in Deep Submicron Technology

In this paper CMOS Four Quadrant Analog Multiplier is designed. It is based on pair of common source amplifier, which acts as input transistor and two identical voltage controlled square root blocks which operate as nonlinear cancellation path. Simulated results using eldo spice in Mentor Graphics Tools for 350nm and 180nm CMOS technology. The main performances of the multiplier including bandwidth, power dissipation, and gain are improved.