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Design and Analysis of 1-bit Full Adder using Different XOR/XNOR Gates with Mentor Graphics
Journal: International Journal for Modern Trends in Science and Technology (IJMTST) (Vol.6, No. 3)Publication Date: 2020-04-30
Authors : G Subhashini V Haribabu P Shravani Raju M Revanth Sai; B Ganesh;
Page : 10-14
Keywords : IJMTST;
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Find it from : Google Scholar
Abstract
In this paper, a 1-bit Full Adder is designed using different XOR/XNOR gates with Mentor Graphics. A Full Adder is implemented using these XOR/XNOR circuits along with a multiplexer. The designed circuits provide full swing voltage and reduces delay as well as power by comparing with 180nm, 130nm, 90nm, 45nm technologies
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Last modified: 2020-05-03 01:47:40