A Novel Approach to FPGA Realization of FIR Filters by Systolization Using Distributed Arithmetic

Distributed arithmetic (DA) is bit serial in nature and is basically re-arrangement of multiply and accumulate operation. In this project we present the design techniques of 1D and 2D fully pipelined computing structures for area, delay, power efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA) based inner-product computation. The systolic decomposition method is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA based computation to decide on suitable area time tradeoff. By using smaller address lengths for DA based computing units, it is possible to reduce the memory size, but on the other hand it leads to increase of adder complexity and the latency. The FIR filter can be realized for different filter orders. The systolic designs can be implemented using Quartus II and MODELSIM and various performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, and energy throughput are estimated for different filter orders and address lengths.