PERFORMANCE ANALYSIS OF RECONFIGURABLE CRYPTO PROCESSOR FOR SECURITY AND PRIVACY IN COMMUNICATION NETWORKSJournal: International Journal of Computer Science and Mobile Computing - IJCSMC (Vol.3, No. 10)
Publication Date: 2014-10-30
Authors : A.Kaleel Rahuman; G.Athisha;
Page : 208-218
Keywords : Advanced Encryption Standard; Data Encryption Standard; Triple DES; Rivest cipher (RC); FPGA;
Recently, the number of electronic devices handling confidential information has increased. In these devices, encryption is applied to protect the confidential information. Therefore, technologies to incorporate cryptographic circuits into these cards have become important. In this work we wish to design the highly securable processor with less power consumption. Cryptographic transformations of AES, 3DES, RC5 are analysed based on the factors like, power consumption, memory usage, speed, number of input/outputs, memory usage. As a result, the algorithm with less power consumption and memory is implemented for designing low power, highly securable crypto processor. These algorithms are computationally intensive, consuming significant power. This paper presents these three algorithms with regard to VHDL and the FPGA. Xilinx software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator, ISE 12.1 suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S200 device of Spartan Family is used for hardware evaluation.
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Last modified: 2014-10-15 19:09:01