COMPARATIVE STUDY OF LOW POWER PULSE TRIGGERED FLIP-FLOP?

Flip-Flops are the critical timing elements in the digital circuits which have large impact on circuit speed and power consumption. The functioning of flip-flop is the important element in determining the efficiency of the system. In this brief a low power flip-flop (FF) based on signal feed through scheme is presented. The proposed design solves the long discharging path problem in conventional explicit type pulse-triggered FF designs and achieves better speed and power performance.