Reconfigured Low Power FPGA Architecture

Field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads is presented in this paper. A low power Asynchronous FPGA with LEDR encoding and 4-Phase dual Rail Encoding is designed in this paper. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. 4-Phase Dual Rail encoding is to achieve small area and LEDR encoding is to get high throughput and low power. LEDR encoding is done at input and 4-phase dual rail encoding is done at the output, which reduces power. Power gating is done to each Logic Block, which shuts down power to the block which is ideal. Power reduction is achieved by selectively setting the functional units into a low leakage mode when they are inactive. The design is synthesized by using Xilinx and programmed using VHDL language and implemented using Xilinx tool. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table.