DESIGN OF RADIX-4 BOOTH MULTIPLIER USING MGDI AND PTL TECHNIQUES

Multiplication is indispensable operation for any high speed digital system, digital signal processors or control system. Primary issues in design of multiplier are area, delay, and power dissipation. Many design architectures and techniques have been developed to overcome these issues. This paper mainly presents radix-4 booth multiplier using MGDI and PTL techniques. The design uses booth encoder, PP-MUX and Ripple carry adder based on MGDI and PTL cells depending upon circuit needs. The multiplier is designed in Tanner EDA tool. The simulation is done using TSMC BSIM 180 nm technology at 1.2v supply voltage. The results are compared with conventional CMOS and GDI techniques. Simulation results show great improvement in terms of area, delay and power dissipation