Design & Implementation of 8x8 Multiplier Unit using MT-CMOS Technique

This paper deals with various multipliers implemented using CMOS logic style and their comparative analysis on the basis of power and PDP (Power delay product). A variety of multipliers have been reported in the literature but power dissipation and area used by these multiplier circuits are relatively large. This paper proposed a high performance and power efficient 8x8 multiplier design based on Vedic mathematics using CMOS logic style. Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The use of Vedas not only abates the carry propagation taking place from lsb to msb but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power than any other type of multipliers in the literature. The proposed MTCMOS implementation of Vedic multiplier is up to 24.55% power efficient and about 98% speedy as compared to the conventional CMOS implementation of Vedic multiplier