Design and Analysis of Routing Algorithm for 3D Network on Chip

Three dimensional network on chip (3D NoC ) is the most thriving on chip connection architecture. According to mesh on-chip conceive approach, investigator favors mesh conceive expertise to analyzed SOCs. That is network on chip mesh architecture has been suggested as solution to address international communication trials in system on chip (SOC) architecture. The performance improvement originating from the architectural benefits of network on chip will be significantly enhanced if 3D ICs are taken up as the rudimentary fabrication methodology. By emerging 3D IC accomplish greater device integration and enhance the system presentation at smaller cost and reduces communication distance in 3D NoC. In addition to its various advantages in terms of power utilization and system performance has possibility to implement an effective architecture. In this paper, effective 3D network on chip architecture is suggested with the mechanism of congestion aware algorithm which optimizes the power utilization, system performance and minimize latency. In supplement we have integrated the reduced cost platform of 3D NoC mesh architecture which can be effectively utilized for fault tolerant and minimized traffic. Based on suggested routing for 3D NoC can help to achieve significant power utilization and minimized the latency.