EFFICIENT FPGA BASED HYBRID CRYPTOGRAPHY ALGORITHM FOR SECURE COMMUNICATION

In this paper, a hybrid cryptography algorithm is proposed. The RSA (Rivest Shamir Adleman) public-key standard has been utilized together with AES (Advanced Encryption Standard), a symmetric key calculation, in this manner strengthening the RSA engineering just as offering ascend to a considerably more secure encryption calculation. This cross breed configuration is actualized on Modelsim to acquire the reenactment results and afterward integrated utilizing Xilinx ISE stage and focused on a FPGA. In the proposed cross breed framework, to give additional security and to accomplish a lot more grounded encryption, the AES key is likewise scrambled utilizing RSA calculation alongside the encryption of plaintext by AES. This for all intents and purposes gives a twofold layer of the security border. For the decoding, the RSA public key is utilized to unscramble the AES key and afterward utilizing this key, the original plaintext message is received.